The present invention relates to a multi-CPU unit which is a programmable controller CPU unit used for industrial equipment and has a plurality of CPU units used for a multi-CPU control operation, and more particularly, to a multi-CPU unit in which the memory capacity can be reduced and the processing speed can be improved.
FIG. 11 is a structural diagram of a conventional multi-CPU unit, and FIG. 12 is a diagram showing the detail of device memories and two-port memories for inter-CPU-unit communication in FIG. 11. Referring to FIG. 11, a CPU unit 1A comprises a microprocessor 2A for transferring data in accordance with information which is obtained by decoding an OS program, an OS 26A for transferring data between a device memory and a two-port memory for communication, a device memory 3A for handling device data, e.g., D0 and D1 in a program which is processed by the CPU unit A, and a two-port memory 24A for inter-CPU-unit communication which communicates data between the CPU units under multi-CPU control operation.
A CPU unit 1B, which has the same configuration as that of the CPU unit 1A, comprises a microprocessor 2B for transferring data in accordance with information which is obtained by decoding an OS program, an OS 26B for transferring data between a device memory and a two-port memory for communication, a device memory 3B for handling device data, e.g., D0 and D1 in a program which is processed by the CPU unit B, and a two-port memory 24B for inter-CPU-unit communication for communicating data between the CPU units under the multi-CPU control operation.
Further, a CPU unit 1C, which has the same configuration as that of the CPU unit 1A, comprises a microprocessor 2C for transferring data in accordance with information which is obtained by decoding an OS program, an OS 26C for transferring data between a device memory and a two-port memory for communication, a device memory 3C for handling device data, e.g., D0 and D1 in a program which is processed by the CPU unit C, and a two-port memory 24C for inter-CPU-unit communication for communicating data between the CPU units under the multi-CPU control operation.
Referring to FIG. 12, the device memory 3A comprises a device data area 10A for CPU unit 1A, a device data area 11A for CPU unit 1B, and a device data area 12A for CPU unit 1C. The two-port memory 24A for inter-CPU-unit communication comprises a data storing area 30A for CPU unit 1B and a data storing area 31A for CPU unit 1C.
The device memory 3B comprises a device data area 10B for CPU unit 1A, a device data area 11B for CPU unit 1B, and a device data area 12B for CPU unit 1C. The two-port memory 24A for inter-CPU-unit communication comprises a data storing area 30B for CPU unit 1A and a data storing area 31B for CPU unit 1C.
Further, the device memory 3C comprises a device data area 10C for CPU unit 1A, a device data area 11C for CPU unit 1B, and a device data area 12C for CPU unit 1C. The two-port memory 24C for inter-CPU-unit communication comprises a data storing area 30C for CPU unit 1A and a data storing area 31C for CPU unit 1B.
FIG. 13 and FIG. 14 are flowcharts showing software which is built in the OSs 26A, 26B,,and 26C in the CPUs and concerns data transfer between the device memories and the two ports for communication. Referring to FIG. 13, first, one is substituted for n so as to determine a CPU-unit number (step S2202), it is checked to see if n coincides with the CPU-unit number of one CPU-7unit (step S2203), the CPU unit is connected to the two-port memory for inter-CPU-unit communication of the CPU unit which is indicated by n if it is determined that n is different from the one CPU unit (step S2204), and further, the block position of the two-port memory for inter-CPU-unit communication to which device data is written is calculated on the basis of the number (steps S2205, S2206, and S2207). After writing the data to the two-port memory for inter-CPU-unit communication, the two-port memory for inter-CPU-unit communication in the CPU unit is separated (step S2208), the next number is obtained (step S2209), and it is checked to see if there are any more CPU units which are used for the multi-CPU control operation (step S2210). If NO, the processing routine is completed (step S2211) and, if YES, the series of the operations is repeated again (steps. S2203 to S2210).
Here, a conventional technique-will be described in accordance with the sequence.
As shown in FIG. 11, the multi-CPU unit comprises the three units of the CPU units 1A, 1B, and 1C. The CPU units 1A, 1B, and 1C comprise the device memories 3A, 3B, and 3C having the device data areas for CPU units 1A, 1B, and 1C, and the two-port memories 24A, 24B, and 24C for inter-CPU-unit communication for communication with the two CPU units other than the one CPU unit of the CPU units 1A, 1B, and 1C, respectively, as shown in FIG. 11.
The CPU units 1A, 1B, and 1C have CPU-unit numbers thereof which are determined by numbers written to the OSs 26A, 26B, and 26C which the CPU units 1A, 1B, and 1C have, respectively. The CPU-unit number gives which number the one CPU unit has under the multi-CPU control operation. Herein, the CPU-unit number of the CPU unit 1A is labeled as 1, the CPU-unit number of the CPU unit 1B as 2, and the CPU-unit number of the CPU unit 1C as 3..
To start with, in order to communicate the contents of the device data area 10A for CPU unit 1A to the CPU unit 1B, the OS 26A connects the CPU unit 1A to the two-port memory 24B for inter-CPU-unit communication in the CPU unit 1B via a communication line 7B. From the CPU-unit number, it is calculated to where the contents of the device data area 10A for CPU unit 1A are to be written in the two-port memory 24B for inter-CPU-unit communication in the CPU unit 1B. According to the calculating method, the CPU-unit number of the one CPU unit is compared with the CPU-unit number of the CPU unit which has the contents to be written, the contents are written to the portion of the CPU-unit number of the one CPU-unit (the portion becomes the first, if the CPU-unit number is 1) if the CPU-unit number of the one CPU unit is smaller, and the contents are written to the portion which is obtained by subtracting one from the CPU-unit number of the one CPU unit (the portion becomes the (2-1)th portion, that is, the first, if the CPU-unit number is 2) if the CPU-unit number of the one CPU unit is larger. Since the CPU-unit number of the CPU unit 1A is land the CPU-unit number of the CPU unit 1B is 2, the CPU-unit number of the CPU unit 1A is smaller. Consequently, the OS 26A in the CPU unit 1A writes the data to the data storing area 30B for CPU unit 1A which exists at the first area in the two-port memory 24B for inter-CPU-unit communication, via a communication line 5A in the CPU unit 1A and the communication line 71 in the CPU unit 1B.
By using a method similar thereto, the OS 26A in the CPU unit 1A writes the data of the device data area 10A for CPU unit 1A in the device memory 3A in the CPU unit 1A to the data storing area 30C for CPU unit 1A in the two-port memory 24C for inter-CPU-unit communication in the CPU unit 1C, via the communication line 5A in the CPU unit 1A and a communication line 7C in the CPU unit 1C.
By using a sequence similar thereto, the OS 26B in the CPU unit 1B writes the data of the device data area 11B for CPU unit 1B in the device memory 3B in the CPU unit 1B to the data storing area 30A for CPU unit 1B in the two-port memory 24A for inter-CPU-unit communication in the CPU unit 1A, via a communication line 5B in the CPU unit 1B and a communication line 7A in the CPU unit 1A. The OS 26B in the CPU unit 1B also writes the data to the data storing area 31C for CPU unit 1B in the two-port-memory 24C for inter-CPU-unit communication in the CPU unit 1C, via the communication line 5B in the CPU unit 1B and the communication line 7C in the CPU unit 1C.
Further, by using a sequence similar thereto, the OS 26C in the CPU unit 1C writes the data of the device data area 11C for CPU unit 1C in the device memory 3C in the CPU unit 1C to the data storing area 31A for CPU unit 1C in the two-port memory 24A for inter-CPU-unit communication in the CPU unit 1A, via a communication line 5C in the CPU unit 1C and the communication line 7A in the CPU unit 1A. The OS 26C in the CPU 1C also writes the data to the data storing area 31B for CPU unit 1C in the two-port memory 24B for inter-CPU-unit communication in the CPU unit 1B, via the communication line 5C in the CPU unit 1C and the communication line 7B in the CPU unit 1B. Thus, the device data of the other CPU-units is written to the two-port memories for inter-CPU-unit communication in the CPU units, respectively.
The foregoing results in transferring to the device memories the device data which is written to the two-port memories for inter-CPU-unit communication in the CPU units. The block 30A as the data storing area for CPU unit 1B in the two-port memory 24A for inter-CPU-unit communication is calculated from the unit number of the CPU unit 1A and the unit number of the CPU unit 1B. The device data area 11A for the CPU unit 1B in the device memory 3A is calculated from the unit number of the CPU unit 1B. The OS 26A in the CPU unit 1A transfers the contents to the device data area 11A for the CPU unit 1B in the device memory 3A in the CPU unit 1A from the data storing area 30A for the CPU unit 1B in the two-port memory 24A for inter-CPU-unit communication in the CPU unit 1A.
Similarly, the device data area 12A for CPU unit 1C in the device memory 3A and the data storing area 31A for CPU unit 1C in the two-port memory 24A for inter-CPU-unit communication are calculated from the unit number of the CPU unit 1C. The OS 26A in the CPU unit 1A transfers the contents of the data storing area 31A for CPU unit 1C to the device data area 12A for CPU unit 1C. This results in the existence of the device data for CPU unit 1A, device data for CPU unit 1B, and device data for CPU unit 1C in the device memory 3A in the CPU unit 1A.
By using the same sequence as that in the case of transferring the data to the device memory 3A from the two-port memory 24A for inter-CPU-unit communication in the CPU unit 1A, the OS 26B in the CPU unit 1B transfers the contents of the data storing area 30B for CPU unit 1A and the data storing area 31B for CPU unit 1C in the two-port memory 24B for inter-CPU-unit communication in the CPU 1B to the device data area 10B for CPU unit 1A and the device data area 12B for CPU unit 1C in the device memory 3B.
By using the same sequence as that in the case of transferring the data to the device memory 3A from the two-port memory 24A for inter-CPU-unit communication in the CPU unit 1A, the OS 26C in the CPU unit 1C transfers the contents of the data storing area 30C for CPU unit 1A and the data storing area 31C for CPU unit 1B in the two-port memory 24C for inter-CPU-unit communication in the CPU 1C to the device data area 10C for CPU unit 1A and the device data area 11C for CPU unit 1B in the device memory 3C.
FIG. 14 shows the transfer operation from the two-port memory for inter-CPU-unit communication to the device memory. First of all, an initial value 1 of the CPU-unit number is substituted for n (step S2302), and it is determined whether or not n is the number of one CPU-unit (step S2303). If NO, n is the number of the other CPU-unit and, therefore, it is determined whether or not this number is smaller/larger than the CPU-unit number of the one CPU-unit (step S2304).
If this number is smaller than the one CPU-unit number, the data is transferred to an n-th block in the device memory from an n-th block in the two-port memory for inter-CPU-unit communication (step S2305). If this number is larger than the number of the one CPU-unit, the data is transferred to the n-th block in the device memory from an (n-l)-th block in the two-port memory for inter-CPU-unit communication (step S2306).
One is added to the CPU-unit number n, thereby calculating the next CPU-unit number (step S2307). It is determined whether or not the number exists in the CPU units under the multi-CPU control operation (step S2308). If the number does not exist, the sequence is completed (step S2309). If the number exists, the series of operations is sequentially executed (step S2303 to step S2308).
According to the above-explained method for communicating the device data under the multi-CPU control operation, it is necessary to have the data storing area for the other CPU-unit except for the one CPU-unit which multi-CPU-controls the CPUs 1A, 1B, and 1C in the two-port memories 24, 24B, and 24C for inter-CPU communication and to write the device data of the one CPU-unit, which corresponds to the number of the other CPU-units, to the data storing areas in the two-port memories for inter-CPU communication. It is also necessary to connect and disconnect the two-port memories for inter-CPU communication which corresponds to the number of CPU-units except for the one CPU-unit which constructs the multi-CPU control. Therefore, if increasing the number of CPU units constructing the multi-CPU, the numbers of connecting times and disconnecting times of the two-port memories for inter-CPU communication increase correspondingly thereto and the processing time increases. Thus, the ratio of time for the control processing, which is inherent, decreases and the response for the control operation deteriorates.
If the number of CPU units constructing the multi-CPU control operation increases, the data storing area in the two-port memory for inter-CPU communication of each CPU unit necessary increases corresponding to the number of CPU units other than the one CPU-unit which constructs the multi-CPU control and a two-port memory for inter-CPU communication having a large capacity is necessitated, thereby raising the costs.
According to the present invention, it is possible to reduce the process for communicating the device data and to save memory in the CPU unit under the multi-CPU control operation by changing the configuration of the data storing area in the two-port memory for inter-CPU communication, which the conventional CPU-unit has.
According to the present invention, there is provided one multi-CPU unit comprising a plurality of CPU units used for multi-CPU control operation, in which each of the CPU units comprises a device memory for handling device data, a shared memory in which data can be read/written from/to each of the CPU-units itself and the other CPU-unit, an OS on which sequence of data transfer is written, and a microprocessor for transferring data between each of the CPU units itself and the other CPU-unit on the basis of the sequence which is written on the OS, wherein each microprocessor reads the device data which is stored in the shared memory of the other CPU-unit to the device memory in each of the CPU-units itself.
The device memory has a device data area for each of the CPU-units itself and a device data area for the other CPU-unit which corresponds to the number of the other CPU-units, and each microprocessor reads the device data which is stored in the shared memory of the other CPU-unit to the device data area for the other CPU-unit in the device memory of each of the CPU-units itself.
According to the present invention, there is provided another multi-CPU unit comprising a plurality of CPU units used for multi-CPU control operation, in which each CPU unit comprises a device memory for handling device data, a shared memory in which data can be read/written from/to each of the CPU-units itself and the other CPU-unit, an OS on which sequence of data transfer is written, and a microprocessor for transferring data between each of the CPU-units itself and the other CPU-unit on the basis of the sequence which is written on the OS, wherein the shared memory has a device data area for each of the CPU-units itself and a device data area for the other CPU-units which corresponds to the number of the other CPU-units and each microprocessor reads the device data of all of the CPU units exclusive of each of the CPU-unit itself, which is stored in the shared memory of the adjacent CPU unit, to the device data area for the other CPU-unit in the shared-memory of each of the CPU units itself.
According to the present invention, there is provided yet another multi-CPU unit comprising a plurality of CPU units used for multi-CPU control operation, in which each of the CPU units comprises a device memory for handling device data, a shared memory in which data can be read/written from/to each of the CPU-units itself and the other CPU-unit, an OS on which sequence of data transfer is written, and a microprocessor for transferring data-between each of the CPU-units itself and the other CPU-unit on the basis of the sequence which is written on the OS, wherein the OS designates a unit number of the other CPU-unit and has a unit-number designating transfer instruction for directly transferring data to the shared memory of the other CPU-unit, and the microprocessor data-transfers the device data of the device memory of each of the CPU units itself to the shared memory of the other CPU-unit by using the unit-number designating transfer instruction.
The shared memory has the device data area for each of the CPU-units itself and the device data area for the other CPU-unit which corresponds to the number of the other CPU-units, and the microprocessor data-transfers the device data of each of the CPU units itself to the shared memory in the other CPU-unit by using the unit-number designating transfer instruction.